Xilinx Vivado compile false warnings

Whenever I come across an Xilinx FPGA tutorial that says: "make sure your design is free of validation errors/warnings", I get skeptical about the writer's experience level, because I've NEVER come across a non-trivial Xilinx design without hundreds of warnings, and a dozen or more critical warnings.  The best I can hope for is to be free of outright errors.  Consider the following critical error in my Vivado design:

[BD 41-967] AXI interface pin /axi_i2s_adi/DMA_ACK_RX is not associated to any clock pin. It may not work correctly.

...

I've been living with this warning ever since I got a Zedboard.  Recently, I finally looked it up on the Xilinx forum.  These are false alarms, according to a Xilinx forum discussion.