 Provide power to USB bus, up to 2 A at V_{bus} = 5 +/0.1V (therefore with effective R_{bus} = 2.5 π), when V_{bat} = 12.6 V.
 Provide power to USB bus, 3 A at V_{bus} = 20 V (therefore with effective R_{bus} = 6.7 π), when V_{bat} = 9.6 V.
 Charge the battery pack (which is at V_{bat} = 11.1 V) from the USB bus, drawing up to 3 A at 20 V. Since R_{bat} = 50 mπ and we want 3A going to the battery, the supply side should be higher than V_{bat} by 150 mV, so we need D V_{bus} = 11.1 + 0.150 = 11.25, so D = 11.25 / 20 = 0.56.
I used Omni Graffle for idea sketch, and LTSpice IV for the schematic capture and simulation (after reading this book on LTSpice).
Switch design
Since the battery voltage will be higher than the 5 V (the output voltage in mode 1) but lower than 20 V (the output voltage in mode 2), neither the pure step down (buck) nor stepup (boost) converter will do the job alone; I need a buckboost converter, which will work like the buck converter if Vbat > Vbus, but like the boost converter when Vbat < Vbus, as you can see below. Buck mode: Vout = D Vin
 Boost mode: Vout = Vin / D'
 Charge mode: Vin = D' Vout
Ignoring losses, in the buck converter mode, the inductor current ripple π«i_{L} ≈ (V_{bat}  V_{bus}) D Ts / 2L. Using the given operating point values in this mode (operating point 1 in the intro),
And again ignoring losses, in the boost converter mode:
π«i_{L} ≈ (12.6  5) 0.4 / (2 100k L) ≈ 15E6 / LAnother way to look at this is to compare against the average inductor current, which must equal the average current to the load: i_{L} ≈ 2 A. The ripple percentage is then π«i_{L }/ I_{L} ≈ 15E6 / L / 2 = 0.75 E6 / L. To hold π«i_{L} within say 10% of the steadystate current then, L must be greater than 0.75 E6 / 10% = 7.5 πH.
And again ignoring losses, in the boost converter mode:
 The voltage ripple at the the output of the converter π«v = V_{bus} D Ts / (2 R_{bus} C), where C is the capacitance in series with the load. If we want π«v < 0.1 V, then C must be larger than V_{bus} D Ts / (2 R_{bus} π«v) = i_{bus} D Ts / (2 π«v) = (3 A) (0.52) (10 πs) / (2 * 0.1) = 78 πF.
 π«i_{L} ≈ V_{bat} D Ts / L which for 10% ripple target means the inductance must be larger than V_{bat} D Ts / (10% 3 A) = 166 πH.
In charging mode, S_{boost} is actually working like a buck switch, so the current ripple analysis can be repeated with voltages flipped numbers: π«i_{L} ≈ (V_{bus}  V_{bat}) D' Ts / 2L. Note that the duty cycle is the complement of the usual buck converter duty cycle, because I am using S_{boost} as the buck converter. For operating point 3, the ratio of the inductor current ripple π«i_{L}/I_{L} then work out to (20 V  11.1 V) 0.555 / (2 10% 100k L). To keep this down below 10% requires L greater than (20  11.1) 0.555 / 20k = 247 πH! The inductor is getting bigger and bigger!
(Solid state) switch design
To implement this schematic with the usual power electronics semiconductor devices, I need the devices Q1~Q4:The "Q" just means some kind of semiconductor device, rather than a transistor necessarily. 
Current flow and voltage across the switches during the D Ts and D' Ts phase of the buck mode 
Current flow and voltage across the switches during the D Ts and D' Ts phase of the boost mode 
Current flow and voltage across the switches during the D Ts and D' Ts phase of the charging mode 
 Q1: active +/passive current, but only + voltage ==> MOSFET in parallel with a diode
 Q2: passive  current, but only + voltage ==> diode
 Q3: active +/passive  current, but only  voltage ==> MOSFET in parallel with a diode
 Q4: active +/passive  current, but only + voltage ==> MOSFET in parallel with a diode
MOSFET choice
I choose Infineon BSC100N03MS as the MOSFET, because it was used in the instructor given examples. According to the data sheet, the drain to source voltage (the blocking voltage) is 30 V, which is sufficient for the maximum of expected 20 V applied on the USB bus end. It is capable of conducting 44 A nominally, and 176 in a pulse. My expected gatesource voltage is 20 V, which is much larger than V_{in} (which is 12.6 V max). In short, it has adequate voltage and current margin for the problem at hand.
S_{buck} implementation using diodes (and a MOSFET)
Q1Q2 pair that comprises S_{buck} has only 1 active element (MOSFET) between them, so the control is rather straightforward (at first), like this:
But since the MOSFET is not grounded, the gate will be floating, so we need a floating gate driver to supply enough current to the gate (to turn it on, or AKA close it) when commanded (c_buck in the schematic below). The floating gate driver in turn needs floating (i.e. isolated) power supply. In this class, a low power isolated unregulated DCDC converter is recommended for use.
The isolated DCDC converter (U8 above) in turn will get the power straight from the battery, and provide V_{outP} − V_{outM} = n V_{in}, where I choose n = 1 (can be between 1 and 2).
Note the resistor between the MOSFET gates and their drivers is there to limit the inrush current into the gate, and should be chosen for the particular MOSFET. But conversely, we want to remove the gate charge from the MOSFET as quickly as possible during the turn off transitionagain as much as the devices can tolerate. So in some examples, I found a Schottky diode (which is a very fast diode with little voltage drop) shorting out the current limiting resistor (as shown below), to effectively remove the current limit during the turn off transition. To be honest, I still don't understand why it's OK to remove current limit when removing the gate charge from the MOSFET, while a current limiting resistor is required when adding it.
S_{boost} implementation using diodes
BUG ALERT: I should have connected outM pin of Uchg_dd to the SOURCE pin of Mchg, but instead connected it to the drain pin. 
MOSFET logic gate coordination
In this realization of the power stage, there are total of 3 MOSFETS that have to be turned on/off in a coordinated manner. Let's enumerate their required on (closed) and off (open) states during the 2 phases in each mode:Mode  Step down (buck)  Step up (boost)  Charge Battery  

Phase  D Ts  D' Ts  D' Ts  D Ts  D' Ts  D Ts 
M_{buck}

1

0

1

1

0

0

M_{boost}

0

0

0

1

0

0

M_{chg}

0

0

0

0

0

1

 Boost = V(control1) > V_{high}/2
 Charge = V(control2) > V_{high}/2
Since the HW recommended a 5 V digital logic, I am using 2.5 V as the threshold. I still need a rapidly switching PWM from these 2 control voltages, so I can derive the PWM signals for the 3 modes like this:
 For stepdown mode, PWM(Vcontrol1), with VM=V_{high}/2, so that M_{buck} duty cycle will be continuous (D = 1) when going from the buck mode to the boost mode.
 For stepup mode, PWM(Vcontrol1  V_{high}/2)
 For charge mode, PWM(Vcontrol2  V_{high}/2)
In cases 2 and 3 above, I need a reference voltage and a subtractor. I am allowed to use an IC to generate a precision reference voltage (despite the irony of having to use a voltage reference in a DCDC converter design); the LT11215 (the "5" in the part name is for 5 V output) was recommended, and I use a voltage divider to derive a 2.5 V from it. With a 1% resistor, I know that the V_{high}/2 reference can be 2 % off (if one resistor is 1% higher and the other is 1% lower), but since the design does not require operation near 100 % duty cycle, I'll be OK. The subtraction of the V_{high}/2 reference voltage can be done with an opamp with sufficiently high openloop gain. I just used the instructor recommended part LT1498 (which has a railtorail inputoutput, 10 MHz gainBW product, and 6 V/us slew rate), as you can see below, where V(Ctrl1_2V5) = V(control1)  Ref2V5.
This subtractor is going to suffer from analog issues (like part and temperature variance). 
The subtracted signal is then fed into a PWM generator with VM=V_{high}/2. The truth table for the MOSFETs can then be implemented with this mixed signal logic:
 duty(M_{buck}) = NOT(control2 > V_{high}/2) AND (control1 > V_{high}/2 OR PWM(control1))
 duty(M_{boost}) = NOT(control2 > V_{high}/2) AND control1 > V_{high}/2 AND PWM(control1  V_{high}/2)
 duty(M_{chg}) = control2 > V_{high}/2 AND PWM(control2  V_{high}/2)
To satisfy both the truth table and the MOSFET duty cycles for the operational points, control2 should be clearly be < V_{high}/2 during buck and boost modes. ANDing the digital signal with PWM's output is necessary because achievable minimum duty cycle may not be 0. The logic IC implements the "> V_{high}/2" operation internally, so I can simplify the above logic expression:
Here is the implementation of duty(M_{buck}), duty(M_{boost}), and duty(M_{chg}) that uses the 5 V and "2.5 V" explained above. duty(M_{buck}) = NOT(control2) AND (control OR PWM(control1))
 duty(M_{boost}) = NOT(control2) AND control1 AND PWM(control1  V_{high}/2)
 duty(M_{chg}) = control2 AND PWM(control2  V_{high}/2)
At first, I use hard coded values for Vcontrol1 and Vcontrol2 to simulate the converter response, so ideally, I want 3 distinct time periods to exercise the 3 operational modes of the converter. That is, I want each of the 3 duty cycles to not overlap. Ignoring noise, it looks like I will be able to do that.
Excessive power loss through the diodes
If I drive the converter in buck mode with duty(M_{buck}) shown above, I can see the expected response of a buck converter.Switch implementation without diodes
From the switch current flow and voltage digram given at the outset, it seems that Q3 and Q4 can each pass current in either direction and block the voltage in a single direction. Therefore, I only need to replace the diode I had used in Q2 with another MOSFET that turns on during the D' interval of the buck mode. Here is the modified switch implementations that can handle all 3 operational modes.
Now that the MOSFETs are doing the double duty, I have to expand the MOSFET truth table to consider the MOSFETs that are complementary to the existing MOSFETs.
The "x" in the truth table means "don't care"; which can be helpful in simplifying the digital logic to implement the truth table:
where I use the prime notation (pwm') to indicate the complement of the duty cycle. Scanning the above Karnaugh chart, it appears that I need both of the boolean signals for control1 and control2. So it's just easier to factor out those common digital logic circuit for reuse.
The 5V and 2.5V reference voltages are shown in a separate part of the schematic:
The NOT(control1) and NOT(control2) are implemented with an offtheshelf inverters.
Then the 2.5V bias subtracted voltages are derived from Ref2V5 and offtheshelf opamps.
The duty cycle and the complementary duty cycle pairs for the buck, boost, and the charge mode are generated by the PWMdeadtime IC pairs; the only differences are the voltage level being commanded. Here, for example, is the PWM pairs for the boost mode:
Finally, the 4 duty cycles can be generated from logic gates. The most complex logic is the 3 AND gates being fed to an OR gate for duty(M_{chg}), but the benefit of carefully building up the intermediate signals pays off.
Step down control1 = 0 control2 = 0 
Step up control1 = 1 control2 = 0 
Charge control1 = 0 control2 = 1 


MOSFET  D Ts  D' Ts  D Ts  D' Ts  D Ts  D' Ts 
M_{buck}  1  0  1  1  1  1 
M_{buck_DP}  0  1  0  0  0  0 
M_{boost}  0  0  1  0  0  1 
M_{chg}  1  1  0  1  1  0 
 duty(M_{buck}) = control2 OR control1 OR pwm(control1)
 duty(M_{buckP}) = NOT(control1) AND NOT(control2) AND pwm'(control1)
 duty(M_{boost}) = (control1 AND pwm(control1  V_{high}/2)) OR (control2 AND pwm'(control2  V_{high}/2))
 duty(M_{chg}) = (NOT(control1) AND NOT(control2)) OR (NOT(control2) AND control1 AND pwm'(control1  V_{high}/2)) OR (control2 AND pwm(control2  V_{high}/2))
The 5V and 2.5V reference voltages are shown in a separate part of the schematic:
The NOT(control1) and NOT(control2) are implemented with an offtheshelf inverters.
Then the 2.5V bias subtracted voltages are derived from Ref2V5 and offtheshelf opamps.
The duty cycle and the complementary duty cycle pairs for the buck, boost, and the charge mode are generated by the PWMdeadtime IC pairs; the only differences are the voltage level being commanded. Here, for example, is the PWM pairs for the boost mode:
I am using the same deadtime of Td = 100ns for all PWM. 
LC filter to damp out voltage ripple
The original power stage design shown above has only one inductor, and a cap each on the input and output ends. There are a few problems with this approach: to reduce the input and output voltage ripple requires huge inductance and capacitance, which in turnsince the natural frequency of LC tank is sort(LC)slows down the transient response. And for some reason, the LiPo battery model given for the project neglects the naturally huge (>> 1 mF) capacitance. If such a large capacitance is modeled, the LC tank would slow down the response unacceptably during the transient to the charging mode. Reducing the L is desirable for speeding up the transient and keeping the part cost down, but the current ripple at the inductor might go above the saturating inductor current.
I think one way to work around the physics of the problem is to put a cascaded LC filter on the input and output side of the power stage, as you can see in this schematic:
L2Cout1 damps out the switching frequency ripple. L2 can easily be an order of magnitude smaller than the main inductor in the power stage. 
By using a small inductorcapacitor combination, the high frequency (at the switching frequency Fs) V_{bus} ripple can be reduced with negligible impact on the slower dynamics of the inner power stage circuit. I want to do the same thing on the input end, but the assignment allows at most 2 inductors, so I held back.
Inductor design
In this assignment, the Ferroxcube 3F3 material (ferrite) is suggested as the core material. Ferrite cores have the HB (electric field intensitytomagnetic field density) nonlinearity depicted below:3 core material properties for the 3F3 are:
 Saturation flux density B_{sat} 0.33T ~ 0.43T, between 25 ΒΊC ~ 100 ΒΊC
 Remnant flux density B_{r} 0.12T
 Coercive force H_{c} ~ 12 A/m (relatively temperature insensitive)
Choosing the inductance value
At first, I tried to use L1 = 247 πH calculated above, and go through the core geometrical constant method (the "K_{g}" method explained in Chapter 14 of the course textbook that I follow in the next section) is used to design the filter inductor L1. But doing that, I wound up with a HUGE inductor (one that weighs hundreds of grams). A USB charging IC is selling for less than $1 at Digikey, so I reasoned that a huge inductor that is an order or magnitude or more expensive than the power management IC is a bad design, and looked for ways to reduce L1. The cascaded LC filter at the USB bus output end I explained earlier. I read the rubric, and actually did not find a requirement for the 10 % current ripple on L1, so I empirically arrived at the L1 and L2 value that met the requirements.
"K_{g}" method
The stepbystep is to enumerate the requirements and constraints on the inductor: Winding material resistivity π Assuming copper at 100 ΒΊC, 2.3E8 πm.
 Desired inductance: L1 = 10 πH, L2 = 1 πH.
 Maximum current I_{max} looks to be about 30 A for L1 (the main inductor) and 30 A for L2 (the isolation inductor).
 B_{max} < B_{sat}, which is a material property of the magnetic core. For ferrite core operating rather hot, B_{sat} = 0.4 T feels reasonable, so B_{max} = 0.3 T.
 Fill factor K_{u} = 0.5 if using notsothin wire.
 R should be determined by acceptable copper loss = I^{2}_{rms} R. Let's say I accept 0.5 W copper loss (1 W through L1 and L2) at 3 A boost or charge mode. Then maximum R = 0.5/3^{2} = 56 mπ for each inductor.
There are other core design that will also meet the K_{g} requirement (like the EE core), but since I don't yet understand the subtleties of core material choice, I am just going with the 1st choice.
The next step is to calculate the required air gap l_{g} (inductors store most of the magnetic energy in the air gap) with this formula: l_{g} = L (π_{0}/A_{c}) (I_{max} / B_{max})^{2}, where π_{0} is the air's magnetic permeability 4π E7 and A_{c} is the core's cross sectional area (0.433 cm^{2} and 0.101 cm^{2} in the above table). Using the values for L1 and L2 above, I get 2.9 mm and 1.24 mm for inductors L1 and L2.
Next, Nthe number of windings around this coreis calculated with N = (L I_{max} ) / (B_{max }A_{c}). I get 23.1 for L1 and 9,9 for L2, so just round them to 23 and 10, respectively. These correspond to A_{L }= L 10^{9} / N^{2}inductance per turn that can be measured while grinding down the core post to create the air gapof 18.7 nH and 10.2 nH for the 2 inductors. A sanity check at this point is to approximate (assuming core permeability π_{c} >> π_{0}) the magnetic flux density B as ≈ π_{0} (N / l_{g}) I; i.e. proportional to the current through the winding and inversely proportional to the air gap. For L1 and L2 calculations made so far, B then approximates to 10 mT times the current, so that at 30 A, B < 0.3 T.
Next, the winding wire cross area A_{wire} should be less than K_{u} W_{A} / N, where W_{A} is the core's window area (bobbin winding area in the above table): 0.187 cm^{2} and 0.097 cm^{2} for the 2 cores chosen. So maximum A_{wire} comes out to 4E3 cm^{2} and 1.7E3 cm^{2} for L1 and L2. In the same Appendix D of the course textbook, table D.6 lists the AWG (American Wire Gauge) specs. From this table, I picked out AWG #22 (A_{wire} = 3.243E3 cm^{2}; diameter 701 πm) and AWG #25 (A_{wire} = 1.6E3 cm^{2}; diameter 505 πm) as being reasonably close to the maximum A_{wire} calculated above. To check that these wire chose does indeed meet the target copper loss, calculate R_{ser} = π N (MLT) / A_{wire}, where MLT is the mean length per turn for the cores given in the above table: 3.71 cm and 2.90 cm for the 1811 and 1408 respectively. So R_{ser} comes out to 60 mπ for L1, and 27 mπ, which are reasonably close to the R_{ser} sought at the beginning. For convenience, here is the comparison of the 2 inductors:
"K_{g} method" formula  L1  L2  

Target inductance L [πH]  Input  10  1 
Target serial resistance R_{ser} [mπ]  Input  56  56 
Target K_{g} [cm^{5}]  (π / R K_{u}) (L I_{max} / B_{max})^{2}  8.2E3  0.082E3 
Offtheshelf K_{g} [cm^{5}]  Textbook Table D.1  9.4E3  0.183E3 
Ferrite pot core size [mm^{2}]  Textbook Table D.1  18x11  9x5 
Core weight [g]  Textbook Table D.1  7.3  1.0 
Cross section area A_{c} [cm^{2}]  Textbook Table D.1  0.433  0.101 
Winding (window) area W_{A} [cm^{2}]  Textbook Table D.1  0.187  0.034 
Magnetic path length l_{m} [cm]  Textbook Table D.1  2.6  1.26 
Air gap l_{g} [mm]  L (π_{0}/A_{c}) (I_{max} / B_{max})^{2}  2.9  1.24 
Number of winding N  round((L I_{max} ) / (B_{max }A_{c}))  23  10 
Inductance per turn A_{L} [nH]  L 10^{9} / N^{2}  18.7  10.2 
B_{scale} [mT/A]  π_{0} (N / l_{g})  10  10 
Maximum A_{wire} [cm^{2}]  K_{u} W_{A} / N  0.187  0.097 
AWG chosen  < Maximum A_{wire}  #22  #25 
AWG A_{wire} [cm^{2}]  3.2E3  1.6E3  
AWG diameter [mm]  0.7  0.5  
Winding resistance R_{ser} [mπ]  π N (MLT) / A_{wire}  60  27 
 L1 node1 node2 Hc=12 Br=0.12 Bs=0.33 A=43u Lm=26m Lg=2.9m N=23 Rser=60m
 L2 node1 node2 Hc=12 Br=0.12 Bs=0.33 A=10u Lm=12.6m Lg=1.24m N=10 Rser=27m
SPICE works in MKS unit, so some mental conversion from the above table is required. I actually found that the "Value" line would not be deleted, so I wrote the SpiceLine on the Value line instead. 
Vbus and Ibus settles quickly to 5 V/2 A and the 20 V/3 A steady state conditions for the buck and boost modes, and the maximum inductor current stays below the saturating current. 
Extra feature: current limiting
Although not plotted above, I found that the current spikes on the battery was approaching 200 Aclearly undesirable (and also physically impossible, due to the huge capacitance that should normally accompany a regular LiPo battery), so I came up with current limiting circuit. The current sense chip I've been drawing above (but not utilizing yet) only detect current in the forward direction, so I threw in another one, like this:
Vcs measures the current in the forward direction, and Mcs measures in the opposite direction. 
I then low pass (1 pole) it before throwing that into a current limit comparator:
The comparator has a large input impedance, so should not load the current sense chip. 
The opposite direction works exactly like above, except for using Mcs as the input. The current limit (iLlim) is hard wired to 90 % of 5 V, or 4.5 V, which should means I will cap the limit to 4.5 V / (20 x 0.01 π) = 22.5 A, which is well below the 30 A saturation limit picked for the main inductor above.
To actually turn off the MOSFETs correctly when the current exceeds the threshold, the digital logic must be changed as follows:
Buck stage complementary signal pair modified for current limitation. 
Boost stage complementary signal pair modified for current limitation. 
I verified in LTSpice that the battery current is now capped at around 25 A, and the inductor current in either direction is also capped at about the same value.
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