JTAG
JTAG only requires 4 pins: clock, data in/out, and mode select (TMS), as shown in this diagram JTAG mode connection to the Xilinx 7 series FPGA:
ug470 describes the implementation of the IEEE 1149.1: TAP (test access port) and boundary-scan architecture, which the industry (and therefore I) call as JTAG in the vernacular. TRST (test reset), enable, VCC, and ground pins sometimes found on the JTAG connectors are apparently optional. There is a TAP controller on the slave side of the JTAG connection, running the IEEE defined state machine, which changes according to the TMS value on the rising edge of TCK.
JTAG looks a lot like SPI: the IN/OUT pins are shifted at every clock, and can even be daisy chained like this:
DRP
Dynamic reconfiguration port is JTAG extension to a PARALLEL read/write MEMORY implemented on some functional blocks of an FPGA. It behaves like many memory devices, having EN, WREN, ADDR, DIN, DOUT, and DRDY pins, as you can see below (also copied from ug470 chapter 4):
JTAG TAP controller converts serial to parallel
ug480 chapter 3, DRP JTAG interface explains the DRP controller that unmarshalls the JTAG DI into the DRP data, as you can see in the case of the XADC block:
So if you only had a JTAG connection available to the peripheral, you COULD serialize the address and data to command the XADC controller. But the DRP controller has minimum wait time between address and data, and between successive writes, as you can see below.
Just as in SPI, the read is a 2-step process: write the desired address, and then shift out the bits.
